1. Field of the Invention
This invention relates generally to voltage regulators, and more particularly to an internally compensated low drop-out (LDO) voltage regulator using a non-inverting variable gain stage to improve stability and optimize power supply rejection ratio (PSRR).
2. Description of the Prior Art
Active compensating capacitive multiplier structures and techniques, e.g. nested Miller compensation, are well known in the art. The specific type of compensating circuit used is dependent upon the particular application. One application of improving phase margin for example, takes advantage of the Miller Effect by adding a Miller compensation capacitance in parallel with an inverting gain stage, e.g., the output stage of a two stage amplifier circuit. Such a configuration results in the well-known and desirable phenomenon called pole splitting, which advantageously multiplies the effective capacitance of the physical capacitor employed in the circuit. See, e.g., for background on compensation of amplifier circuits using Miller-compensating capacitance, Paul R. Gray and Robert g. Meyer, Analysis and Design of Analog Integrated Circuits, Third Ed., John Wiley & sons, Inc. New York, 1993, Ch. 9, especially pp. 607-623.
Recent trends associated with high efficiency battery powered equipment are creating increased demand for power management systems using DC/DC converters feeding low drop-out (LDO) voltage regulators. Applications requiring power from such LDO voltage regulators are becoming more sensitive to noise as application bandwidth requirements are pushed ever upward. This places far greater importance on the power supply ripple rejection (PSRR) characteristics associated with LDO voltage regulators since LDO voltage regulators are used to both clean up the output noise of the DC/DC converter and to provide power supply cross talk immunity from application blocks sharing the same raw DC supply.
There is also a trend showing an increased use of ceramic capacitors as output decoupling capacitors as contrasted with the once more typical use of tantalum capacitors in such applications. The significantly low equivalent series resistance (ESR) associated with ceramic capacitors however, makes reliance on ceramic output capacitor ESR characteristics no longer feasible to stabilize an LDO amplifier control loop. Thus, a need exists in the LDO amplifier art for an internal compensation technique allowing use of a wide range of output capacitor types. Such internal compensation techniques would allow the use of much smaller output capacitors and therefore provide a means for reducing both PCB real estate requirements and external component costs.
One widely popular accepted technique associated with internal compensation is known as "Pole splitting" or "Miller Compensation" such as discussed herein above. Miller compensation, however, provides an impedance shunt across the series pass device associated with LDO voltage regulators, via the compensation capacitor and Cgs. This impedance is undesirable since it causes an early roll-off in PSRR.
Some conventional two-stage PMOS low drop-out voltage regulators suffer from very poor load regulation at light, or no load, conditions. This is due to the gate of the PMOS series pass being driven from a source follower, Vdsat+Vgs, where Vt can vary from +0.2 to -0.2V for a natural NMOS device and +0.5 to +0.9V for a standard device. Such variations will ultimately force the first stage amplifier output devices to enter their triode region (linear mode) when the regulator is lightly loaded, resulting in a significant reduction in loop gain and hence deterioration in regulator performance.
The basic architecture for a PMOS voltage regulator includes an error amplifier to drive a power PMOS transistor, that supplies load current anywhere from zero up to hundreds of milli-amperes. Generally, a very large external filter capacitor (micro-farad range), is connected at the output node to improve transient response when load current changes quickly and dramatically. A block diagram of this basic architecture is shown in FIG. 1.
Due to its special application, a PMOS voltage regulator has very unique load-dependent open loop frequency response characteristics. Under high supply voltage and minimum load current conditions, the power PMOS transistor operates in its sub-threshold region which produces a very large output impedance (hundreds of kilo-ohms range or more), wherein the output node will generate a low frequency pole. Under low supply voltage and maximum load current conditions, the PMOS transistor is well into its triode region in which the output impedance is extremely low (tens of ohms or less), wherein the pole at the output node is pushed out to the kilohertz range. The decades of movement associated with the pole presents significant design challenges, especially regarding stability compensation.
Given the nature that the foregoing LDO is basically a two-stage amplifier, using a Miller capacitor for compensation is a very attractive approach. Tying a capacitor C.sub.c from the output node V.sub.out to the gate input N_PG of the PMOS transistor however, does not provide a desirable solution for two reasons: First, the two poles might not be separated far enough. For example, if the dominant pole is at N_PG due to the Miller effect, having a frequency at ##EQU1##
then the second pole comes in at a frequency of ##EQU2##
The distance between the two poles is: ##EQU3##
CFILT is generally much larger than C.sub.c (50,000 times larger if CFILT is 4.7 .mu.F and C.sub.c is 90 pF. Even if the product of G.sup.2.sub.mMPO.multidot.r.sub.oMPO.multidot.r.sub.oAMP is large which basically equals the gain of a two-stage amplifier, f.sub.pd and f.sub.p2 are still not too far apart. Thus, the circuit will either suffer too poor phase margin or too low open-loop gain. Actually, it is possible that at low load current, the dominant pole is very likely at V.sub.out ; and at high load current, when G.sub.mMPO is significantly larger, the dominant pole is then at N_PG. Thus, an even worse scenario can occur somewhere along the load current in which the two poles are closest to each other resulting in a "pole swapping" point.
Second, the C.sub.c will degrade the PSRR performance. A simple way to look at this characteristic is: the C.sub.c in series with CFILT to ground directly loads the error amplifier, so when the ripple frequency on the supply line increases, the impedance from N_PG to ground decreases, which effectively "clamps" the gate voltage of MPO referenced to ground. The gate voltage will therefore not be able to track the ripples injected into the MPO source. This directly modulates the V.sub.gs of MPO and therefore also V.sub.out.
In view of the foregoing, a need exists for an amplifier circuit architecture and technique capable of achieving better stability and higher PSRR performance from an internally compensated PMOS low drop-out voltage regulator than that presently achievable using conventional "Miller" or "Pole-splitting" techniques presently known in the art.